The present invention relates to methods for fabricating a semiconductor device, and particularly to methods for fabricating a semiconductor device which includes a semiconductor layer containing silicon (Si) and a group IV element other than Si (referred hereinafter to as a contaminant).
With recent progress in performance enhancement and size reduction of mobile communication devices, transistors mounted in a semiconductor device are required to provide high-frequency operation in a higher frequency band and high-speed operation with lower power consumption. As a solution capable of satisfying such requirements, for example, a conventional method of fabricating a semiconductor device with a heterojunction bipolar transistor as described below is known.
FIGS. 5A through 8B are sectional views illustrating process steps in an exemplary conventional method of fabricating a semiconductor device having a heterojunction bipolar transistor.
First, in the step shown in FIG. 5A, a p-type semiconductor substrate 200 is prepared which is made of single crystal silicon whose principal plane is the (100) plane having a resistivity of 10 to 15 Ω·cm, for example. The semiconductor substrate 200 is subjected to ion implantation using a resist film (not shown) as an implantation mask, and thus an n-type buried layer 201 is formed in a bipolar-transistor formation region of the semiconductor substrate 200. After the removal of the resist film and the heat treatment for the substrate, a silicon crystal layer is epitaxially grown to form an n-type epitaxial layer 202 on the main surface side of the substrate.
Next, trenches deeper than the buried layer 201 are formed in regions located at the main surface side of the semiconductor substrate 200 and alongside of the buried layer 201. By thermal oxidation, the surfaces of the deep trenches are oxidized. A polysilicon film 203 is then deposited over all surfaces of the substrate. The resulting polysilicon film 203 is etched back, thereby providing the deep trenches filled with the polysilicon film 203.
In the step shown in FIG. 5B, a resist film 204 having shallow-trench formation regions opened therein is formed, and the semiconductor substrate 200 is etched using this resist film as an etching mask. As a result, shallow trenches 205 are formed to the main surface side of the semiconductor substrate 200.
Subsequently, in the step shown in FIG. 5C, a first silicon oxide film 206 is deposited to the main surface side of the substrate, after which planarization of the deposited film is performed by chemical-mechanical polishing (referred hereinafter to as CMP) or the like. As a result, all the shallow trenches 205 are filled with the first silicon oxide film 206. An N-type dopant is then implanted into the contact portion of the substrate with a metallic collector electrode to form a collector connecting layer 207.
In the step shown in FIG. 5D, a second silicon oxide film 208 is deposited over all surfaces of the substrate, and then a first polysilicon film 209 is deposited on the second silicon oxide film 208. Then, a resist film 210 having an opening therein is formed to the main surface side of the substrate. The second silicon oxide film 208 and the first polysilicon film 209 are patterned by etching using this resist film as a mask, thereby forming a collector opening Aco. In the opening Aco, a base formation region of the bipolar transistor exists.
Next, in the step shown in FIG. 6A, selective epitaxial growth is performed to form a p-type intrinsic base layer 211 containing a SiGe layer and a Si layer on the base formation region. During the growth, p-type polycrystalline Si/SiGe films 212 are also formed to the main and back surface sides of the substrate. When the intrinsic base layer 211 is grown to have a great thickness, the growth selectivity would break down, resulting in the growth of the polycrystalline Si/SiGe film 212 on the silicon oxide film as well. This undesirable growth may lead to the occurrence of particles causing the failure of semiconductor elements. In order to avoid this, the first polysilicon film 209 as a seed layer for the polycrystalline Si/SiGe film 212 is often formed in advance.
Next, in the step shown in FIG. 6B, a third silicon oxide film 213 is deposited over all surfaces of the substrate.
In the step shown in FIG. 6C, a resist film 214 is formed to the main surface side of the substrate, and etching is made using this resist film as a mask such that the third silicon oxide film 213 is allowed to remain on the center portion of the intrinsic base layer 211 and on the Si/SiGe film 212.
In the step shown in FIG. 6D, a p-type polysilicon film 215 is deposited over all surfaces of the substrate, after which a fourth silicon oxide film 216 is deposited on the polysilicon film 215.
In the step shown in FIG. 7A, a resist film 217 is formed to the main surface side of the substrate. By etching using this resist film as a mask, the polysilicon film 215 and the fourth silicon oxide film 216 are patterned. Thus, an emitter opening Aem is formed and the center portion of the third silicon oxide film 213 is exposed at the bottom of the emitter opening Aem.
In the step shown in FIG. 7B, a fifth silicon oxide film 218 is deposited over all surfaces of the substrate, and then an n-type polysilicon film 219, for example, is formed on the fifth silicon oxide film 218. The fifth silicon oxide film 218 and the polysilicon film 219 are etched back. The resulting fifth silicon oxide film 218 and polysilicon film 219 are allowed to remain as side walls on the sides of the emitter opening Aem.
By wet etching, a portion of the third silicon oxide film 213 exposed at the bottom of the emitter opening Aem is removed to expose the center portion of the intrinsic base layer 211. At the time, the Si/SiGe film 212 which is formed on the first polysilicon film 209 is also exposed. Note that the edge of the fifth silicon oxide film 218 is also etched and set back due to this wet etching.
Next, in the step shown in FIG. 7C, an n-type polysilicon film 220 is formed over all surfaces of the substrate, and then the substrate is subjected to heat treatment by rapid thermal annealing (RTA) or the like. The heat treatment diffuses the n-type dopant contained in the polysilicon film 220 into the intrinsic base layer 211, thereby forming an emitter layer 221.
In the step shown in FIG. 8A, a resist film 222 is formed to the main surface side of the substrate. By etching using the resist film 222 as a mask, the polysilicon film 220, the fifth silicon oxide film 218 and the fourth silicon oxide film 216 are patterned, and the resulting polysilicon film 220 is used as an emitter connecting electrode. During this patterning, the first polysilicon film 209 and the Si/SiGe film 212, which are formed on the second silicon oxide film 208, are also patterned, and the resulting first polysilicon film 209 and polysilicon film 215 are used for a base connecting electrode.
Subsequently, in the step shown in FIG. 8B, a sixth silicon oxide film 223 as an interlayer insulating film is deposited to the main surface side of the substrate, after which the surface of the sixth silicon oxide film 223 is planarized by CMP or the like. Contact holes are then formed in portions of the sixth silicon oxide film 223 by photolithography and etching. Finally, a film made of an aluminum alloy (an Al alloy film) is deposited by sputtering in the contact holes and on the sixth silicon oxide film 233 and the sputtered Al alloy film is patterned by photolithography and etching, thereby forming Al wiring 224.
With the foregoing steps, a semiconductor device including a heterojunction bipolar transistor is obtained. Although not shown in FIGS. 5A through 8B, a CMOS device may be formed on the semiconductor substrate 200 apart from the bipolar transistor.
In a conventional method for fabricating a semiconductor device, a wafer which contains a contaminant, such as germanium (Ge), adversely affecting the characteristics of a Si device is generally processed separately from a wafer containing no contaminant by providing a dedicated fabrication line. This separate process is very common in fabricating a semiconductor device such as a DRAM. More specifically, the device fabrication is broadly separated into: the process steps free from contamination (master process); the process steps using tungsten silicide or the like which causes a middle level of contamination damage (siliciding process); and the process steps using aluminum, copper or the like which causes a high level of contamination damage (interconnecting process). In each process, dedicated semiconductor fabrication equipment processes the wafer.
The formation of such fabrication lines is made implementable by the fact that a high volume of semiconductor devices are manufactured using such fabrication lines and therefore a high rate of operation of the semiconductor fabrication equipment can be set. With the conventional semiconductor-device fabrication lines, however, no device fabrication has been made by processing wafers containing a contaminant and wafers containing no contaminant while sharing almost all fabrication equipment in a common fabrication line. The reason for this is to avoid the deterioration in the performance of the fabricated semiconductor device due to contamination.
Heterojunction devices including a Si/SiGe heterojunction (hereinafter, referred simply to as “SiGe devices”) can function as semiconductor devices with a high performance owing to germanium contained therein. Since germanium is a contaminant for CMOS devices, however, it is necessary to build a dedicated line for the fabrication of the SiGe devices, as described above. If the dedicated line for the SiGe devices is not provided, the quality of gate oxide films of the fabricated devices or the reliability of the fabricated devices may be deteriorated. For example, where a 20 nm-thick gate oxide film is formed on each wafer and Qbd (charge to breakdown) at which the cumulative failure rate for the wafer is 50% is measured, the wafer forcedly contaminated with germanium (Ge content: 2.5 to 8×1012 atoms/cm2) has a Qbd of 0.2 to 0.9 C/cm2. This value is remarkably smaller than that of the wafer free from contamination, that is, 2.0 to 3.0 C/cm2 (Ge content: less than 1×109 atoms/cm2, which is the sensitivity limit). It is found from these values that the contaminated wafer has a poor breakdown voltage.
However, provision of a dedicated fabrication line to fabricate SiGe devices without adversely affecting Si devices would bring many cost disadvantages for products fabricated in large item small volume production, which is impractical.
Moreover, SiGe devices are generally fabricated in a fabrication line one or more generation older than CMOS devices. The reason for this is as follows. Very expensive fabrication equipment is used in the fabrication line requiring the cutting edge of fine patterning, so that a high depreciation cost would be required for that equipment. This restricts the use of the fabrication line only to the fabrication of CMOS devices which would promise a high operation rate. On the contrary, the fabrication of SiGe devices in such a cutting-edge line would be a large economic burden because it is unlikely to promise a high operation rate. For this reason, mass-production SiGe devices lag behind CMOS devices in performance enhancement by fine pattering.
As is apparent from the above, in fabricating a SiGe device in an existing fabrication line shared with the fabrication of other devices such as a CMOS device, there exist the following problems. Specifically, in the conventional fabrication step of a semiconductor device shown in FIG. 6A, if the p-type intrinsic base layer 211, which is formed by selective epitaxial growth, contains a contaminant such as germanium, the p-type Si/SiGe film 212 formed to the back surface side of the substrate also contains germanium as a contaminant. When, in the wafer of the structure shown in FIG. 6A, the thickness of the epitaxial growth layer is measured or the wafer is checked by a microscope, germanium contained in the film 212 may be a source of contamination and adhere to another wafer through a stage, robot arm, vacuum wand and the like of the measurement equipment or the check equipment. As a result, germanium adhered to that wafer may cause subsequent contamination (referred hereinafter to as “secondary contamination”).
Furthermore, in the case where the third silicon oxide film 213 is formed by LP-CVD in the step shown in FIG. 6B or in the case where the n-type polysilicon film 220 is formed by LP-CVD in the step shown in FIG. 7C, secondary contamination may occur through a tube, boat and wafer loader in a furnace.
Likewise, in the case where the silicon oxide film 213 is subjected to wet etching in the step shown in FIG. 7B, or in the case where the p-type Si/SiGe film 212 to the main surface side of the semiconductor substrate is subjected to dry etching in the step shown in FIG. 8A, secondary contamination may occur through an etching bath, chamber, wafer loader and the like.